ZBT (zero bus turnaround) is a synchronous SRAM architecture optimized for a switching function and a router function that require frequent and highly random read and write operations, for example, in networking and telecommunications applications. A ZBT SRAM device is useful for removing an idling state that might be encountered during access to a data bus through which switching between write and read operations is frequently performed. In other words, the ZBT SRAM device removes a dead cycle and enables use in a maximum memory bandwidth.
While a DRAM device requires a periodic refresh operation and a pre-charge operation for a bit line, an SRAM device is excellent in terms of a data access cycle. In the SRAM device, each cell is composed by four or six transistors. In a high resistive load type cell, the four transistors are constituted of two selection transistors connected to a pair of bit lines and two transistors having their gates and drains cross-connected to each other, while a CMOS type cell is constituted from the six transistors. The DRAM device is constituted from one transistor and one capacitor. It means that a DRAM is superior to an SRAM in a die area, power dissipation, and a cost. Thus, there is proposed an enhanced bus turnaround DRAM which aims at improvements in device integration, power dissipation, and the cost as well as provides advantages of a conventional ZBT SRAM device having a pin arrangement, timing and function similar to those of the SRAM (refer the following reference 1 (termed as a Patent Document 1)).
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2001-283587A (p. 2, FIG. 1)
A memory device described in the above Patent Document 1 includes a WAIT signal output pin that informs to a controller outside the memory device that a memory array is in a state which cannot be used for data access. The above Patent Document 1 describes an object of providing the enhanced bus turnaround DRAM with the pin arrangement, the timing, and function sets similar to those of the ZBT SRAM device and having same advantages as the ZBT SRAM device. However, the device is not ZBT-SRAM compatible. In the above Patent Document 1, use of a two-port DRAM cell is not described, and a usual one-port DRAM cell is considered to be used. There is a need to always insert a refresh cycle between read/write cycles; and in the refresh cycle, read/write operations must be interrupted. When the DRAM is applied to communications, specifications for enabling continuous read/write operations are required. In such communications applications, the conventional ZBT SRAM cannot be replaced by the enhanced bus turnaround DRAM described in the above Patent Document 1. In a paragraph [0059] in a detailed description of the above Patent Document 1, there is such a description that when the refresh cycle is hidden behind a readout cycle of a cache, an effect of almost every refresh cycles on the operation of the memory device is made minimum. However, in case where read/write requests for data not on the cache in the memory array continually occur, even though the occurrence of such a case is not frequent, the read/write operations had to be interrupted by using the WAIT terminal, as a result of which the ZBT SRAM cannot be replaced by the enhanced bus turnaround DRAM.
On the other hand, as shown in FIG. 11, there is known a dynamic random access memory (refer the following reference 2 (Patent Document 2), for example). This memory includes a cell array which has a plurality of memory cells, each of which is a two-port DRAM cell. In each two-port memory cell, first and second switch transistors 205 and 206 are connected in series between a bit line 201 for normal access and a bit line 202 for refreshing only. A capacitor element 207 for storing data is connected to a connection node at which the first and second switch transistors 205 and 206 are tied. A word line 204 for normal access and a word line 203 for refreshing are connected to respective control terminals of the first and second switch transistors 205 and 206. In this memory, when an external memory access and a refresh are made in a overlapped timing to an identical address, the refresh is masked.
There is also known a memory (refer the following reference 3 (Patent Document 3), for example). In this memory, the two-port DRAM cells shown in FIG. 11 are employed; and bit lines dedicated for write and bit lines dedicated for read are provided, and read and write operations are simultaneously performed. For a refresh, cell data is read from the corresponding bit line dedicated for read, and amplified by a sense amplifier. Then, the cell data is written back through the corresponding bit line dedicated for write.
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-3-263685 (p. 2, FIG. 2)
[Patent Document 3]
JP Patent No. 2653689 (p. 3, FIG. 2)